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NXP Semiconductors /LPC18xx /SCT /FRACMAT5

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Interpret as FRACMAT5

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0FRACMAT_L 0RESERVED0FRACMAT_H 0RESERVED

Description

Fractional match registers 0 to 5 for SCT match value registers 0 to 5.

Fields

FRACMAT_L

When UNIFY = 0, read or write the 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_L register (n = 0 to 5). When UNIFY = 1, the value applies to the unified, 32-bit fractional match register.
RESERVED

Reserved.
FRACMAT_H

When UNIFY = 0, read or write 4-bit value specifying the dither pattern to be applied to the corresponding MATCHn_H register (n = 0 to 5).
RESERVED

Reserved.

Links

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Register Reference

https://github.com/cmsis-svd/cmsis-svd-data